In the traditional I/O model, a host computing system interfaces with its peripheral I/O devices when executing accelerator tasks or functions using custom I/O device drivers unique to the peripheral I/O device. Having multiple I/O devices or even multiple instances of the same I/O device means that the host interfaces with multiple I/O device drivers or multiple running copies of the same I/O device driver. This can result in security and reliability issues since the I/O device drivers are typically developed by the vendor supplying the peripheral I/O devices but must integrate with all the software and hardware in the host computing system.
Meanwhile, the hardware cache-coherent shared-memory multiprocessor paradigm leverages a generic, instruction set architecture (ISA)-independent, model of interfacing in the execution tasks or functions on multiprocessor CPUs. The generic, ISA-independent (e.g., C-code) model of interfacing scales with both the number of processing units and the amount of shared memory available to those processing units. Traditionally, peripheral I/O devices have been unable to benefit from the coherent paradigm used by CPUs executing on the host computing system.